Introduction to Vias

In brief, each hole on the PCB can be called vias. From the point of view of function, vias can be divided into two categories: one is used as an electrical connection between the layers, and two is used as a device for fixing or positioning.

If the process from the process, these vias are generally divided into three categories, namely blind hole (blind via), via(buried) and through hole(through via). The blind hole is located on the top and bottom surface of the printed circuit board and has a depth that is used for the connection of the surface line and the inner line below. The depth of the hole usually does not exceed a certain ratio. A burried hole means a connecting hole in the inner layer of a printed circuit board, which does not extend to the surface of the circuit board. The two types of holes are located in the inner layer of the circuit board, and are complete by using the through hole forming process before lamination, and may be overlapped in the process of hole formation, so as to make a few inner layers. The third is called through holes, which pass through the entire circuit board and can be used for internal interconnection or as mounting holes for components. Since vias are easier to implement and lower in cost, most printed circuit boards use it without two other vias.

The vias mentioned below (without special instructions), are considered as vias. From the design point of view, a hole is made up of two main parts: one is the middle hole(drill hole), and the other is the pad area around the borehole. The size of these two sections determines the size of the vias. Obviously, in the high speed and high density PCB design, designers always hope through holes as small as possible, so the board can have more wiring space. In addition, if a hole is small, the parasitic capacitance is smaller, more suitable for high speed circuit. But the decreasing pore size also brings cost increases, and the hole size cannot be reduced without limit.

It is drilling(drill) and electroplating(plating) technology limited: 1) the smaller the hole drilling takes longer, the easier to deviate from the center position and 2) when 6times the depth of the hole over the hole diameter, hole wall cannot guarantee uniform copper plating. For example, the thickness of a normal 6pcs PCB board(through hole depth) is about 50mil, so the diameter of the drill hole provided by the PCB manufacturer is the smallest, and can only reach 8mil.

The parasitic capacitance through hole vias exists on the parasitic capacitance. If the isolation hole diameter hole in the ground layer seen on D2, a hole pad diameter is D1, PCB plate thickness T, substrate dielectric constant epsilon. The parasitic capacitance of the vias is approximately the same as that of C=1.41 eplison TD1/(D2-D1), and the parasitic capacitance of the vias causes the main effect on the circuit to prolong the signal rise time and reduce the speed of the circuit. For example, for a 50mil plate thickness is PCB, if you use the 10mil inner diameter, hole diameter of 20mil pad, pad and floor area copper distance is 32mil, the parasitic capacitance we can through the above formula calculated through hole is roughly: C=1.41*4.4*0.05*0.02/(0.032-0.02)=0.517pf, the partial capacitance rise caused by time variation: T10-90=2.2C(Z0/2)=2.2*0.517*(55/2)=31.28ps. From these values can be seen, despite the rise of parasitic capacitance single hole of the delay caused by the slow effect is not very obvious. But if you walk the line repeatedly vias switching between layers, or the designer should consider carefully.

Three, the parasitic inductance vias. Vias exist at the same time there is a parasitic capacitance and parasitic inductance, in the design of high speed digital circuit, harm parasitic inductance vias caused by parasitic capacitance is often greater than its parasitic series inductance will weaken the contribution of bypass capacitor and weaken the filtering effectiveness of the whole power supply system. We can use the following formula to simply calculate an over hole approximation of parasitic inductance: L=5.08h[1n(4h/d)+1], WHERE L refers to the inductance of the through hole, h is the length of the through hole, and D is the diameter of the center bore. It can be seen from the formula that the diameter of the through hole has little influence on the inductance, and the length pf the through hole is the most influential factor on the inductance. The above example is still used to calculate the inductance of the vias: L=5.08*0.05[1n(4*0.05/0.01)+1]=1.015nh. If the signal rise time is 1ns, then the equivalent impedance is XL=PI L/T10-90=3.19 ohms. It has a high frequency current through the impedance cannot be ignored, in particular, bypass capacitor through two holes in the connection of power and ground planes, it will increase on the parasitic inductance of hole.

Through hole design through above on the through hole parasitic characteristics analysis of four high speed PCB, we can see that in the high-speed PCB design, seemingly simple holes will often bring a negative effect to the circuit design. In order to reduce the adverse effects caused by the parasitic effect of vias, we can do as much as possible in design: 1, From the two aspects of cost and signal quality, we should select the size of the through-hole of reasonable size. For example, the 6-10layer memory module PCB design, the use of 10/20mil(drilling/pad) through the hole is better. For some high-density small size of the board, you can also try to use 8/18mil through the hole. At present, it is difficult to use smaller size vias under technical conditions. For power or ground vias, a larger size may be considered to minimize impedance. 2, the two formulas discussed above can be used to reduce the two parasitic parameters of vias by using thinner PCB plates. 3, PCB signal on the boards as far as possible without changing the layer, that is to say, do not use unnecessary vias. 4, power and ground pins to close through the hole. The power and ground lead should be as thick as possible to reduce the impedance. 5, Some ground vias are placed near the vias of the signal transfer layer to provide the closest loop for the signal. You can even place a number of redundant ground vias on the PCB board.

Of course, flexibility is needed in design. The cross hole model discussed above is a pad for each layer, and sometimes we can reduce or even remove some layers of pads. Especially in the hole density is very large, may lead to a broken circuit partition groove is formed on a copper layer, to solve this problem in addition to move the position of the hole, we can also consider a decrease in the size of the hole pad copper layer.